NXP Semiconductors /NeoM3 /CCAN /MSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MSR

CAN Central Miscellaneous Register

E1	When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)
E2	When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)
RESERVED	Reserved, the value read from a reserved bit is not defined.
BS1	When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR).
BS2	When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR).
RESERVED	Reserved, the value read from a reserved bit is not defined.

()